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[[Image:]] Spirit Level Board
Summary This document describes the test procedures for testing the Altium Spirit Level Board REV1.01.

.

Test Specification TS0100 (v1.0) January 13, 2005

Abstract

This document assumes that the Device Under Test (DUT) has undergone the standard practice manufacturing QA steps including:

  • PCB bare board testing
  • Component incoming goods inspections
  • Parts issue verification
  • Visual inspection for component placement and soldering defects

There are several levels of test setups, depending on the additional test hardware available:

On-Board Voltage Regulation Test

This test should be performed before the DUT is connected to any external hardware. It checks for the integrity of the on-board voltage rails.

It requires:

  • Current limited power supply unit (PSU) with voltage and current meter
  • Digital Multi-Meter (DMM)

Crystal Oscillator Frequency Test

This test verifies that the DUT has the correct crystal oscillator fitted.

It requires:

  • Frequency counter

On-Board FPGA Programming

This test verifies that the FPGA (U1) can be successfully programmed via the Altium DXP 2004 software. It requires a PC running the Altium DXP 2004 software, an Altium JTAG Universal Connector, and the appropriate cables.

Interactive Functional Tests

These tests verify the sub-sections of the spirit level board, including: the LCD, the push button, DIP switches, LEDs, User Headers, and the accelerometer device. Some can be performed without additional hardware, while the User Header test requires a loop-back cable.

Table 1on the following page shows what functional blocks can be tested with the different test setups.

Configuration Device test

Under normal in-service use, the configuration device (U5) programs the FPGA on power-up. This test will verify that the configuration device can be programmed via the DXP 2004 software, and that the configuration device can then program the FPGA on power-up.

Test Setup requirements


Test Setup requirements for each test
 Test Page J-TAG Universal Connector & cables Voltmeter/Ammeter Bench Power Supply Power supply & cable Loopback cable Frequency counter Shorting link
Power Supply and Rail Regulators
3
Power Toggle Switch
3
Power Indicator LED
3
Crystal Oscillator Frequency
4
FPGA programming (U1)
5
LCD Display
7
LCD Backlight
Test/Reset Button
7
User LEDs (LED[0..7])
7
User Headers
7
Accelerometer
8
Configuration device (U5)
10

Table 1. Test setups for the various tests performed in this test specification

  1. On-Board Voltage Regulation Test

This test must be performed before any other hardware is connected to the DUT. It is performed to make sure that no catastrophic faults in the power supply exist that could potentially damage external hardware.

Test Setup

This test uses the Laboratory Power Supply Unit (PSU) to power the DUT while the voltage rails are checked.

Parts required

  • Variable Laboratory Power Supply Unit (PSU) with integrated voltage and current meters and variable current limit.
  • Cable with DC jack, wired centre positive to connect PSU to J1 on DUT
  • Digital Multi-Meter (DMM)

Test Procedure

  1. Remove all cabling from the DUT.
  2. Set PSU output voltage to 5V0.2V
  3. Short out PSU output and set current limit to 1A.
  4. Connect PSU jack to J1 on DUT and verify on the PSU that current is 150mA 100mA in the ‘ON’ position and <0.1mA in the ‘OFF’ position, otherwise disconnect and reject DUT.
  5. Toggle On/Off switch S1 and verify the functionality of power LED9 (Figure 1-1), otherwise disconnect PSU and reject DUT.
  6. Connect negative lead of multimeter to a GND pin on the DUT, for example either pin on JP6, and verify the voltage at TP1 (Figure 1-2) is 5V0.2V, otherwise disconnect PSU and reject DUT.
  7. Verify the output voltage at TP2 (Figure 1-3) is 3.30.1V, otherwise disconnect PSU and reject DUT.
  8. Verify the output voltage at TP3 (Figure 1-4) is 1.80.08V, otherwise disconnect PSU and reject DUT.

[[Image:|thumb|Figure 1. Connection points for on-board voltage regulation tests]]

  1. Crystal Oscillator Frequency Test

This test will verify that the crystal oscillator is outputting the correct frequency.

Test Setup

This test uses the Spirit Level power supply to power the DUT while the oscillator frequency is checked.

Parts Required

  • Spirit Level power supply
  • Frequency counter, capable of measuring 25MHz

Test Procedure

  1. Turn off S1 (switch toggle should be closer to J1), and connect Spirit Level power supply to J1.
  2. Connect ground lead from the frequency counter to a GND pin on the DUT, for example JP6.
  3. Using a suitable probe fitted to the frequency counter, touch pin 3 of Y1 to measure the Crystal Oscillator output frequency, as shown in Figure 2. The measured frequency should be 25MHz 25ppm

[[Image:]]

Figure 2. Checking the output frequency of the crystal oscillator.


  1. Programming the FPGA

This test will program the Xilinx Spartan XC2S300E FPGA on the DUT.

Test Setup

This test uses the J-TAG Universal Connector (JUC1) to interface the DUT to the DXP 2004 software running on the PC. If you have not previously used DXP 2004 for testing the DUT, refer to the section Preparing the Test PC and Test Project at the end of this specification for more information on set up.

Parts Required

  • PC running DXP 2004
  • Spirit Level Power Supply
  • J-TAG Universal Connector board (JUC1, Rev1.01 or higher)
  • PC NanoTalk Parallel Port Cable (26-way flat ribbon, DB25F / 26-way header)
  • User Board Cable (10-way flat ribbon, 10-way header / 10-way header)
  • Shorting Link(standard 0.1” pitch)

Test Procedure

  1. Connect JUC1 to the computer’s parallel port, using the 26-way PC NanoTalk Parallel Port Cable.
  2. Connect JUC1 to DUT (HDR1), using the 10-way User Board cable.
  3. Turn off S1 (switch toggle should be closer to J1), and connect Spirit Level power supply to J1.
  4. Fit a Shorting Link to the CONFIG jumper.
  5. Turn on S1 to power up DUT.
  6. Start DXP 2004 software on PC and load the project FPGA_SL1_Tester.PrjFpg, if not already loaded. Select View » Devices and verify the Connected indicator status is green, as shown in Figure 3-1.

[[Image:]]

Figure 3. Stages of programming the FPGA on the Spirit Level board.

  1. Confirm that the correct project and configuration is currently targeting the FPGA, Figure 3-2 shows where this information appears in the Devices view, it should say SpiritLevel / Target_2E.
  2. The Compile, Synthesize and Build buttons should also display a green status indicator, if they do not refer to the section Preparing the Test PC and Test Project at the end of this specification for more information on how to set up the project correctly. If these buttons are all green then click the Program FPGA button, as shown in Figure 3-3.
  3. Programming the FPGA will take a some time, the status indicator at the bottom of the software will show the progress, as shown in Figure 3-4.
  4. Once device programming is complete the status indicator on the Program FPGA button will change to green (Figure 4-1), the TSK51A_D icon in the centre of the display will show a status of Running, as shown in Figure 4-2, and the DONE LED on the DUT board will turn on.

[[Image:]]

Figure 4. Devices view once the FPGA has been successfully programmed.

Reaching this point indicates that the FPGA has been successfully programmed, this stage of the test process is now complete. The test software has also been loaded by this process, and the Interactive Functional Tests can now be run.

  1. Interactive Functional Tests

Once the FPGA has been programmed, a series of self tests can be run, as described below.

Test Setup

The following section describes the test setup required for running all of the functional tests. Note that the User Header test will fail if the Loopback cable is not connected.

Parts Required

  • PC running DXP 2004
  • Spirit Level Power Supply
  • J-TAG Universal Connector board (JUC1, Rev1.01 or higher)
  • PC NanoTalk Parallel Port Cable (26-way flat ribbon, DB25F / 26-way header)
  • User Board Cable (10-way flat ribbon, 10-way header / 10-way header)
  • User Header Loopback cable (20-way flat ribbon, 20-way header / 20-way header)
  • 2 Shorting Links (standard 0.1” pitch)

Test Procedure

  1. Program the FPGA using the process described in the previous section, On-Board FPGA Programming. Once this has been done the functional tests can be run.
  2. Before running any tests the contrast on the LCD must be set, adjust the Contrast potentiometer R1 until the text shown below is just visible on the LCD. If this text does not appear reject DUT.

Adjust ContrastPress TEST/RESET

    1. Push Button Test
  1. Once the contrast has been set, press the Test/Reset button (S3). This test will verify that the push button is operating correctly, and will start the LCD test.
    1. Liquid Crystal Display (LCD) Module and LED Test
  1. The LCD will cycle through the full character set, verify that there are no gaps in the character sequences.
  2. At the same time each of the eight LEDs (LED0 to LED7) on the DUT will turn on and off one after the other, verify that each of the eight LED lights up independently of all of the other LEDs.
    1. DIP Switch Test

When the LCD and LED test is complete, the LCD will display the following text:

DIP Switches12345678

  1. Starting with switch 1 on the DIP switch (S2), cycle each dip switch in turn (turn it on and then off). You must turn the switch off before switching the next one on. The LCD will indicate which of the switches has been tested successfully (the switch number will be replaced by a block character). Also, each LED will light as each DIP switch is turned on.
    1. User Header Test

When the DIP Switch test is complete, the LCD will display the following text:

DIP SwitchesPASSED - RESET

Fit the 20-way loop back cable between HRD2 and HDR3 to prepare for the User Header test.

  1. Press the Test/Reset button S3 to start the User Header Loopback test, the LCD will indicate if the test has passed/failed.
    1. Accelerometer Test

When the User Header test is complete, the LCD will display the following text:

User IOsPASSED - RESET

  1. The accelerometer will now be calibrated, ensure that it is sitting on a flat, horizontal surface, and press the Test/Reset button S3 to perform the calibration. During calibration the LCD will display

CalibratingX/Y AXIS…

Once calibration is complete the LCD will display:

Calib. CompletedPress TEST/RESET

  1. Press the Test/Reset button S3 to Start the accelerometer X axis measure.
  2. Lift the left-hand end of the DUT to so that the board forms an approximate angle of 30 degrees (in the X-axis), and confirm that the angle 30º is displayed on the LCD (plus or minus up to 3º is acceptable).
  3. Press the Test/Reset button S3 to Start the accelerometer Y axis measure.
  4. Tip the board toward you to so that the board forms an approximate angle of 30 degrees (in the Y-axis), and confirm that the angle -30º is displayed on the LCD (plus or minus up to 3º is acceptable).
    1. Accelerometer Jumper Test
  1. Return the DUT to the flat, horizontal surface.
  2. Press the Test/Reset button S3 to move to the X Jumper test. The LCD will display:

Jumper on X AxisPress TEST/RESET

  1. Fit shorting links to the jumpers JP3.
  2. Press the Test/Reset button S3 to start the accelerometer X Jumper test. Confirm that the following message appears on the LCDX Axis From HA3??º
  3. Lift the left-hand end of the DUT to so that the board forms an approximate angle of 30 degrees (in the X-axis), and confirm that the angle 30º is displayed on the LCD (plus or minus up to 3º is acceptable).
  4. Press the Test/Reset button S3 to move to the Y Jumper test. The LCD will display:

Jumper on Y AxisPress TEST/RESET

  1. Fit shorting links to the jumpers JP4.
  2. Press the Test/Reset button S3 to start the accelerometer Y Jumper test. Confirm that the following message appears on the LCDY Axis From HA5??º
  3. Tip the board toward you to so that the board forms an approximate angle of 30 degrees (in the Y-axis), and confirm that the angle -30º is displayed on the LCD (plus or minus up to 3º is acceptable).
    1. Completion of Interactive Functional Tests
  1. When the Accelerometer Jumper Test is complete, press the Test/Reset button S3.
  2. Confirm that the following message is displayed on the LCD:

- SUCCESS - RESET To Restart

The Interactive Functional Tests are now complete.

Configuration Device Test

This test verifies that the Configuration device, U5, can be programmed from the DXP 2004 software, and that U5 can then correctly program the FPGA on power-up.

Test Setup

This test uses the J-TAG Universal Connector (JUC1) to interface the DUT to the DXP 2004 software running on the PC. If you have not previously used DXP 2004 for testing the DUT, refer to the section Preparing the Test PC and Test Project at the end of this specification for more information on set up.

Parts Required

  • PC running DXP 2004
  • Spirit Level Power Supply
  • J-TAG Universal Connector board (JUC1, Rev1.01 or higher)
  • PC NanoTalk Parallel Port Cable (26-way flat ribbon, DB25F / 26-way header)
  • User Board Cable (10-way flat ribbon, 10-way header / 10-way header)

Test Procedure

  1. Connect JUC1 to the computer’s parallel port, using the 26-way PC NanoTalk Parallel Port Cable.
  2. Connect JUC1 to DUT (HDR1), using the 10-way User Board cable.
  3. Turn off S1 (switch toggle should be closer to J1), and connect Spirit Level power supply to J1.
  4. Remove the Shorting Link from the CONFIG jumper.
  5. Turn on S1 to power up DUT.
  6. Start DXP 2004 software on PC. Select View » Devices and verify the Connected indicator status is green, as shown in Figure 5-1, and the 2 devices (the Spartan 2E FPGA, XC2S300E-6PQ208C and the XCF Config device, XCF02SSVO20C) are present, as shown in Figure 5-2.

[[Image:]]

Figure 5. Preparing to program the configuration device, U5

  1. To program the configuration device, right-click on the XCF component and select Choose File and Download from the floating context menu, as shown in Figure 6.

[[Image:]]

Figure 6. Selecting the program file for the configuration device

  1. Locate and select the file ConfigTest.MCS in the Choose Programming File for Xilinx XCF dialog, as shown in Figure 7, and click the Open button to close the dialog and start the process.

[[Image:]]

Figure 7. Choosing the program file

  1. After this dialog closes the Confirm dialog will appear, as shown in Figure 8, click Yes to Verify the Programming.

[[Image:]]

Figure 8. Click yes to Confirm that the device is to be programmed.

  1. The programming status will be reported on the Status bar at the bottom of the DXP 2004 workspace, it may take a few minutes to complete the programming. When it is complete an information dialog will appear (as shown in Figure 9), reporting if the programming was successful, as shown in .

If the programming failed turn the power to the DUT off, and then on again, and repeat the programming process. Typically the Configure device should program on the first attempt, but for certain PC/ribbon cable combinations it can take a number of attempts.

[[Image:]]

Figure 9. Information dialog reporting if the device has programmed sucessfully

  1. Check that there is no Shorting Link fitted to the Config header.
  2. Once the Config device has been successfully programmed turn the power to the DUT off, and then on again. If the Config device correctly programs the FPGA on power up, the following message will appear on the LCD.

SpiritLevel V1.0Press Test/Reset

  1. Press the Test/Reset button S3, the LCD display will change to display the current X and Y angles:

X axis angle ??ºY axis angle ??º

Testing of the Spirit Level board is now complete.

Preparing the Test PC and Test Project

Abstract

Programming the FPGA on the DUT must be done via the DXP 2004 software, with the appropriate project open.

Preparing the DXP 2004 software

Once the DXP 2004 software is installed from the installation CD it must be activated (licensed). This is done by choosing DXP » Licensing from the menus, and then clicking on the Activate License using the Web link that is displayed.

To complete this process you will be required to enter your company number and the activation code, both of which are supplied with the software.

Preparing the Test Project

The Spirit Level board is tested using the test project, FPGA_SL1_Tester.PrjFpg. Complete the following steps to prepare the test project. Note that this process is described as if there is no Altium-FPGA-ready board currently connected to the PC. If there is a JUC1 and Spirit Level board connected then you will not need to manually add the FPGA device, but will still need to verify if the project outputs are ready.

  1. Open the project FPGA_SL1_Tester.PrjFpg.
  2. Select View » Devices from the menus to display the Devices view.

What is displayed in the Devices view can depend on if there is an Altium-FPGA-ready board currently connected to the PC, or what FPGA device was present in the last FPGA project that was open in DXP 2004.

  1. Right-click in the centre region of the view to display the Add context menu, and choose XC2S300E-6PQ208C (Spirit Level/Target_2E), as shown in Figure 10.

[[Image:]]

Figure 10. Add the target device into the Devices view

  1. To use this project for testing, the appropriate project outputs must be present. If they are, all the indicators will show green, if any of the indicators do not show green (as shown in Figure 11), the Build button must be clicked to process the design and generate the project outputs.

[[Image:]]

Figure 11. Project outputs not ready for use, click Build to regenerate them

  1. When all the indicators show green (as shown in Figure 12), the project outputs are ready to download into a Spirit Level board (DUT) for testing.

[[Image:]]

Figure 12. Indicators all green, the project outputs are ready for download into DUT.

Revision History


Date Version No. Revision
13-Jan-2005 1.0 New product release

Software, documentation and related materials:

Copyright © 2005 Altium Limited.

All rights reserved. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, DXP, Design Explorer, nVisage, Nexar, Protel, P-CAD, Tasking, CAMtastic, Situs and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed.









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